OskiBear 28nm RISC-V BLE Chip

OskiBear 28nm RISC-V BLE Chip

OskiBear is a TSMC 28nm HPC chip that is $1mm^2$ in die area. This is a demonstration of agile chip development enabled by open source technologies and research infrastructure around RISC-V.

The chip has a in-house developed bluetooth modem, baseband, and AES accelerators. The compute complex of the chip and all of the digital component are generated through Chipyard and Chisel. Through Chisel and Chipyard, we can leverage high performance open source deisgns such as RocketChip, standard peripherals, and the surrounding software ecosystem. The chip runs at 20MHz and should be able to run at 50MHz (though at 50MHz the ADC may not work). The compute capabilities including a 24K DTIM, 16K I$, 32bit FPU, hardware accelerated AES, memory mapped and cached QSPI flash through SPI XIP (execute in place), GPIO, JTAG, and UART.

This chip demonstrates it is possible to tape-out a BLE chip on a decently modern technology node (28nm HPC) with a small team of 20 undergraduates and a few experienced PhD students.

In this project, I was mainly tasked with specing the compute complex, design the layout of the digital part of the chip, and simulation and verification of the compute functionailities. It's simply astonishing that we as a team can go from basically clueless to taping out a chip in a little more than 3 month, and I would not have thought that I can contribute to the physical design work with my super limited background. (I'm more of a graphics and maybe micro architecture person)

Here is the layout of the entire chip, maybe a real die shot can be put here when the chip come back from TSMC in later August.

More details on this experience should be added here, hopefully soon?